Publications

JOURNAL PAPERS

  1. O. Ahmed, C. Okoro, S. Pollard and T. Jiang, “The Effect of Materials and Design on the Reliability of Through-Glass Vias for 2.5D Integrated Circuits: A Numerical Study”, Multidiscipline Modeling in Materials and Structures, in press, 2020.
  2. O. Ahmed, C. Okoro, S. Pollard and T. Jiang, “The Interfacial Reliability of Through Glass Vias for 2.5D Integrated Circuits”, Microelectronics International, 37 (4), pp. 181-188 (2020).
  3. O. Ahmed, G. Jalilvand, C. Okoro, S. Pollard and T. Jiang “Micro-Compression of Free-Standing Electroplated Copper Through-Glass Vias”, IEEE Trans. on Device and Materials Reliability, IEEE Trans. on Device and Materials Reliability, 20 (1), pp. 199-203 (2020).
  4. Spinella, J. Im, T. Jiang and P.S. Ho, “Synchrotron X-ray Microdiffraction Investigation of Scaling Effects on Reliability for Through-silicon Via (TSV) in 3D Integration”, IEEE Trans. on Device and Materials Reliability, 19 (3), pp. 568-571 (2019).
  5. Jalilvand, O. Ahmed, L. Spinella, L. Zhou and T. Jiang, “The effective control of Cu through-silicon via extrusion for three-dimensional integrated circuits by a metallic cap layer”, Scripta Materialia, 165, pp. 101-104 (2019).
  6. Spinella, T. Jiang, J. Im, and P.S. Ho, “Correlation of Through-silicon Via (TSV) Dimension Scaling to TSV Stress and Reliability for 3D Interconnect”, Advancing Microelectronics Magazine, 44(2), pp. 12-15 (2017) (cover story).
  7. T. Jiang, L. Spinella, J. Im, R. Huang, P. S. Ho, “Processing Effect on Via Extrusion for TSVs in Three-Dimensional Interconnects: A Comparative Study”, IEEE Trans. on Device and Materials Reliability, 16 (4), pp. 465-469 (2016).
  8. X. Chen, C. Dejoie, T. Jiang, C.-S. Ku and N. Tamura, “Quantitative Microstructural Imaging by Scanning Laue X-Ray Micro- and Nanodiffraction”, MRS Bulletin, 42 (6), pp. 445-453 (2016) (invited review paper).
  9. A. Cho, F. Shafiei, B.S. Mendoza, M. Lei, T. Jiang, P. S. Ho, and M. C. Downer, “Second-harmonic Microscopy of Strain Fields around Through-Silicon-Vias”, Appl. Phys. Lett., 108, 151602 (2016).
  10. Y. Hao, L. Wang, Y. Liu, H. Chen, X. Wang, C. Tan, S. Nie, J. W. Suk, T. Jiang, T. Liang, J. Xiao, W. Ye, C. R. Dean, B. I. Yakobson, K.F. McCarty, P. Kim, J. Hone, L. Colombo, and R.S. Ruoff, “Oxygen-Activated Growth and Bandgap Tunability of Large Single-Crystal Bilayer Graphene”, Nature Nanotechnology, 11, pp. 426–431  (2016).
  11. T. Jiang, C. Wu, J. Im, R. Huang, P. S. Ho, “Impact of Grain Structure and Material Properties on Via Extrusion in 3-D Interconnects”, Journal of Microelectronics and Electronic Packaging, 12, pp. 118-122 (2015).
  12. T. Jiang, J. Im, R. Huang, and P.S. Ho, “TSV Stress Characteristics and Reliability Impact for 3D Integrated Circuits”, MRS Bulletin, 40 (3), pp 248 – 256 (2015) (invited review paper).
  13. T. Jiang, C. Wu, N. Tamura, M. Kunz, B. G. Kim, H-Y. Son, M.-S. Suh, J. Im, R. Huang, and P. S. Ho, “Study of Stresses and Plasticity in Through-Silicon Via Structures for 3D Interconnects by X-Ray Micro-Beam Diffraction”, IEEE Trans. on Device and Materials Reliability, 14(2), pp. 698-703 (2014).
  14. S.K. Ryu, T. Jiang, J. Im, R. Huang, and P.S. Ho, “Thermomechanical Failure Analysis of Through-Silicon Via Interface Using a Shear-Lag Model With Cohesive Zone”, IEEE Trans. on Device and Materials Reliability, 14(1), pp.318-326 (2014).
  15. T. Jiang, C. Wu, L. Spinella, J. Im, N. Tamura, M. Kunz, H-Y. Son, B. G. Kim, R. Huang, and P.S. Ho, “Plasticity Mechanism For Copper Extrusion In Through-Silicon Vias for Three-Dimensional Interconnects”, Appl. Phys. Lett., 103, 211906 (2013).
  16. T. Jiang, S.K. Ryu, Q. Zhao, J. Im, R. Huang, and P.S. Ho, “Measurement and Analysis of Thermal Stresses in 3D Integrated Structures Containing Through-Silicon-Vias”, Microelectron Reliab., 53, pp. 53-62 (2013).
  17. S.K. Ryu, K.H. Lu, T. Jiang, J. Im, R. Huang, and P.S. Ho, “Effect of Thermal Stresses on Carrier Mobility and Keep-out Zone around Through-Silicon Vias for 3-D Integration”, IEEE Trans. on Device and Materials Reliability, 12, 255-262 (2012).
  18. S.K. Ryu, T. Jiang, K.H. Lu, J. Im, H.-Y. Son, K.-Y. Byun, R. Huang, and P.S. Ho, “Characterization of Thermal Stresses in Through-Silicon Vias for Three-Dimensional Interconnects by Bending Beam Technique”, Appl. Phys. Lett., 100, 041901 (2012).

CONFERENCE PROCEEDINGS

  1. G. Jalilvand, O. Ahmed, N. Dube and T. Jiang, “Study of the Impact of Pitch Distance on the Statistical Variation of TSV Extrusion and the Underlying Mechanism”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp.1173-1179 (2020).
  2. A. Ahari, O. Ahmed, P. Su, B. Glasauer, T. Jiang and T.-K. Lee, “An Effective and Application-Specific Evaluation of Low-k Integration Integrity using Cu Pillar Shear Testing”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp.1517-1524 (2020).
  3. Ahmed, G. Jalilvand, H. Fernandez, J. Dieguez, T.-K. Lee, P. Su, and T. Jiang, “Long-Term Reliability of Solder Joints in 3D Memory ICs under Near-Application Conditions”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 1106-1112 (2019).
  4. Jalilvand, O. Ahmed, L. Zhou and T. Jiang, “Study of the Effect and Mechanism of a Cap Layer in Controlling of the Statistical Variation of Via Extrusion”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 1909-1915 (2019).
  5. Ahmed, G. Jalilvand, J. Dieguez, P. Su, and T. Jiang, “Study of the Long Term Reliability of 3D IC under Near-Application Conditions”, ”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 476-482 (2018).
  6. G. Jalilvand, O. Ahmed, K. Bosworth, Z. Pei, C. Fitzgerald, and T. Jiang, “Application of a Metallic Cap Layer to Control Cu TSV Extrusion”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 61-66 (2017).
  7. L. Spinella, T. Jiang, J. Im, and P.S. Ho, “Synchrotron X-ray Microdiffraction Investigation of Scaling Effects on Plasticity and the correlation to TSV Extrusion” Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 752-757 (2017).
  8. L. Spinella, T. Jiang, M. Park, N. Tamura, J. Im, P.S. Ho, “Effect of Scaling Copper Through-Silicon Vias on Stress and Reliability for 3D Interconnects”, Proc. 2016 IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), pp. 80-82 (2016).
  9. T. Jiang, C. Wu, P. Su, P. Kim, C. Bassett, K. Sichak, J. Gandhi, J. Li, J. Im, R, Huang, and P. S. Ho, “Investigation of Thermo-mechanical Stresses and Reliability of 3D Die-Stack Structures by Synchrotron X-ray Micro-diffraction”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 1718 – 1724 (2015).
  10. T. Jiang, C. Wu, J. Im, R. Huang, and P.S. Ho, “Effect of Microstructure on Via Extrusion Profile and Reliability Implication for Copper Through-Silicon Vias (TSVs) Structures”, Proc. IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), pp. 377-380 (2014).
  11. T. Jiang, C. Wu, P. Su, P. Chia, L. Li, H.-Y. Son, M.-S. Suh, N.-S Kim, J. Im, R. Huang, and P.S. Ho, “Effect of High Temperature Storage on the Stress and Reliability of 3D Stacked Chip”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 1122 – 1127 (2014).
  12. T. Jiang, S.K. Ryu, J. Im, R. Huang, and P.S. Ho, “Characterization of Thermal Stresses and Plasticity in Through-silicon Via Structures for Three-dimensional Integration”, AIP Conf. Proc. 1601, 55 (2014).
  13. T. Jiang, S.K. Ryu, Q. Zhao, J. Im, P.S. Ho, and R. Huang, “Thermomechanical Characterization and Modeling for TSV Structures”, AIP Conf. Proc. 1601, 148 (2014).
  14. T. Jiang, S.K. Ryu, J. Im, H.-Y Son, N.-S. Kim, R. Huang, and P.S. Ho, “Impact of Material and Microstructure on Thermal Stresses and Reliability of Through-Silicon Via (TSV) Structures”, Proc. International Interconnect Technology Conference (IITC), pp. 1-3 (2013).
  15. T. Jiang, C.L. Wu, P. Su, X. Liu, P. Chia, L. Li, H.-Y. Son, N.-S. Kim, K.-Y. Byun, J.-S. Oh, J. Im, R. Huang, and P.S. Ho, “Characterization of Plasticity and Stresses in TSV Structures in Stacked Dies Using Synchrotron X-ray Microdiffraction”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 641 – 647 (2013).
  16. T. Jiang, S.K. Ryu, Q. Zhao, J. Im, H.-Y. Son, K.-Y Byun, R. Huang and P.S. Ho, “Thermal stress Characteristics and Impact on Device Keep-out Zone for 3-D ICs Containing Through-silicon-vias”, IEEE Symposium on VLSI Technology (VLSIT),  pp. 103-104 (2012).
  17. T. Jiang, S.K. Ryu, Q. Zhao, J. Im, H.-Y. Son, K.-Y Byun, R. Huang, and P.S. Ho, “Measurement and Analysis of Thermal Stresses in 3-D Integrated Structures Containing Through-Silicon-Vias”, Proc. IEEE International Interconnect Technology Conference (IITC), pp.1-3 (2012).
  18. T. Jiang, S.K. Ryu, Q. Zhao, J. Im, H.-Y. Son, K.-Y. Byun, R. Huang, and P.S. Ho, “Thermal Stress Characteristics and Reliability Impact On 3-D ICs Containing Through-Silicon-Vias”, Proc. IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp.1-3 (2012).
  19. Wang, S.-H. Chae, R. Dunne, Y. Takahashi, K. Mawatari, P. Steinmann, T. Bonifield, T. Jiang, J. Im, P.S. Ho, “Effect Of Intermetallic Formation on Electromigration Reliability of TSV-Microbump Joints in 3D Interconnect”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 319- 325 (2012).

BOOK CHAPTERS

  1. Chen, T. Jiang, and X. Fan, “Die- and Package-Level Modeling and Characterization of Thermal and Thermal/Moisture Stresses in 3-D Packaging: Modeling and Characterization”, 3D Microelectronic Packaging: From Fundamentals to Applications, Y. Li & D. Goyal Eds., pp 293-332 (2017). Springer International Publishing, Switzerland.
  2. S.K. Ryu, T. Jiang, J. Im, R. Huang and P.S. Ho, “Thermal Stress in 3-D Packaging”, Encyclopedia of Thermal Stresses, R.B. Hetnarski Ed., pp 5208-5217 (2014). Springer Dordrecht, Heidelberg, New York, London.
  3. Fu-Zhai Cui and Teng-Fei Jiang, “Tissue-Engineered Bone”, Wiley Encyclopedia of Biomedical Engineering, M. Akay Ed.,(2006). John Wiley & Sons, Hoboken, New Jersey.