JOURNAL PAPERS

- O. Ahmed, C. Okoro, S. Pollard and
__T. Jiang__, “The Effect of Materials and Design on the Reliability of Through-Glass Vias for 2.5D Integrated Circuits: A Numerical Study”, Multidiscipline Modeling in Materials and Structures, in press, 2020. - O. Ahmed, C. Okoro, S. Pollard and
__T. Jiang__, “The Interfacial Reliability of Through Glass Vias for 2.5D Integrated Circuits”, Microelectronics International, 37 (4), pp. 181-188 (2020). - O. Ahmed, G. Jalilvand, C. Okoro, S. Pollard and
__T. Jiang__“Micro-Compression of Free-Standing Electroplated Copper Through-Glass Vias”,*IEEE Trans. on Device and Materials Reliability*, IEEE Trans. on Device and Materials Reliability, 20 (1), pp. 199-203 (2020). - Spinella, J. Im,
__T. Jiang__and P.S. Ho, “Synchrotron X-ray Microdiffraction Investigation of Scaling Effects on Reliability for Through-silicon Via (TSV) in 3D Integration”,*IEEE Trans. on Device and Materials Reliability*, 19 (3), pp. 568-571 (2019). - Jalilvand, O. Ahmed, L. Spinella, L. Zhou and
__T. Jiang__, “The effective control of Cu through-silicon via extrusion for three-dimensional integrated circuits by a metallic cap layer”,*Scripta Materialia*, 165, pp. 101-104 (2019). - Spinella,
__T. Jiang__, J. Im, and P.S. Ho, “Correlation of Through-silicon Via (TSV) Dimension Scaling to TSV Stress and Reliability for 3D Interconnect”,*Advancing Microelectronics Magazine*, 44(2), pp. 12-15 (2017) (cover story). __T. Jiang__, L. Spinella, J. Im, R. Huang, P. S. Ho, “Processing Effect on Via Extrusion for TSVs in Three-Dimensional Interconnects: A Comparative Study”,*IEEE Trans. on Device and Materials Reliability,*16 (4), pp. 465-469 (2016).- X. Chen, C. Dejoie,
__T. Jiang__, C.-S. Ku and N. Tamura, “Quantitative Microstructural Imaging by Scanning Laue X-Ray Micro- and Nanodiffraction”,*MRS Bulletin,*42 (6), pp. 445-453 (2016)*(invited review paper)*. - A. Cho, F. Shafiei, B.S. Mendoza, M. Lei,
__T. Jiang__, P. S. Ho, and M. C. Downer, “Second-harmonic Microscopy of Strain Fields around Through-Silicon-Vias”,*Appl. Phys. Lett.*, 108, 151602 (2016). - Y. Hao, L. Wang, Y. Liu, H. Chen, X. Wang, C. Tan, S. Nie, J. W. Suk, T. Jiang, T. Liang, J. Xiao, W. Ye, C. R. Dean, B. I. Yakobson, K.F. McCarty, P. Kim, J. Hone, L. Colombo, and R.S. Ruoff, “Oxygen-Activated Growth and Bandgap Tunability of Large Single-Crystal Bilayer Graphene”,
*Nature Nanotechnology,*11, pp. 426–431 (2016). __T. Jiang__, C. Wu, J. Im, R. Huang, P. S. Ho, “Impact of Grain Structure and Material Properties on Via Extrusion in 3-D Interconnects”,*Journal of Microelectronics and Electronic Packaging*, 12, pp. 118-122 (2015).__T. Jiang__, J. Im, R. Huang, and P.S. Ho, “TSV Stress Characteristics and Reliability Impact for 3D Integrated Circuits”,*MRS Bulletin*, 40 (3), pp 248 – 256 (2015)*(invited review paper)*.__T. Jiang__, C. Wu, N. Tamura, M. Kunz, B. G. Kim, H-Y. Son, M.-S. Suh, J. Im, R. Huang, and P. S. Ho, “Study of Stresses and Plasticity in Through-Silicon Via Structures for 3D Interconnects by X-Ray Micro-Beam Diffraction”,*IEEE Trans. on Device and Materials Reliability*, 14(2), pp. 698-703 (2014).- S.K. Ryu,
__T. Jiang__, J. Im, R. Huang, and P.S. Ho, “Thermomechanical Failure Analysis of Through-Silicon Via Interface Using a Shear-Lag Model With Cohesive Zone”,*IEEE Trans. on Device and Materials Reliability*, 14(1), pp.318-326 (2014). __T. Jiang__, C. Wu, L. Spinella, J. Im, N. Tamura, M. Kunz, H-Y. Son, B. G. Kim, R. Huang, and P.S. Ho, “Plasticity Mechanism For Copper Extrusion In Through-Silicon Vias for Three-Dimensional Interconnects”,*Appl. Phys. Lett.*, 103, 211906 (2013).__T. Jiang__, S.K. Ryu, Q. Zhao, J. Im, R. Huang, and P.S. Ho, “Measurement and Analysis of Thermal Stresses in 3D Integrated Structures Containing Through-Silicon-Vias”,*Microelectron Reliab.*, 53, pp. 53-62 (2013).- S.K. Ryu, K.H. Lu,
__T. Jiang__, J. Im, R. Huang, and P.S. Ho, “Effect of Thermal Stresses on Carrier Mobility and Keep-out Zone around Through-Silicon Vias for 3-D Integration”,*IEEE Trans. on Device and Materials Reliability*, 12, 255-262 (2012). - S.K. Ryu,
__T. Jiang__, K.H. Lu, J. Im, H.-Y. Son, K.-Y. Byun, R. Huang, and P.S. Ho, “Characterization of Thermal Stresses in Through-Silicon Vias for Three-Dimensional Interconnects by Bending Beam Technique”,*Appl. Phys. Lett.*, 100, 041901 (2012).

CONFERENCE PROCEEDINGS

- G. Jalilvand, O. Ahmed, N. Dube and
__T. Jiang__, “Study of the Impact of Pitch Distance on the Statistical Variation of TSV Extrusion and the Underlying Mechanism”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp.1173-1179 (2020). - A. Ahari, O. Ahmed, P. Su, B. Glasauer,
__T. Jiang__and T.-K. Lee, “An Effective and Application-Specific Evaluation of Low-k Integration Integrity using Cu Pillar Shear Testing”, Proc. IEEE Electronic Component and Technology Conference (ECTC), pp.1517-1524 (2020). - Ahmed, G. Jalilvand, H. Fernandez, J. Dieguez, T.-K. Lee, P. Su, and
__T. Jiang__, “Long-Term Reliability of Solder Joints in 3D Memory ICs under Near-Application Conditions”,*Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 1106-1112 (2019).* - Jalilvand, O. Ahmed, L. Zhou and
__T. Jiang__, “Study of the Effect and Mechanism of a Cap Layer in Controlling of the Statistical Variation of Via Extrusion”,*Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 1909-1915 (2019).* - Ahmed, G. Jalilvand, J. Dieguez, P. Su, and
__T. Jiang__, “Study of the Long Term Reliability of 3D IC under Near-Application Conditions”, ”,*Proc. IEEE Electronic Component and Technology Conference (ECTC), pp. 476-482 (2018).* - G. Jalilvand, O. Ahmed, K. Bosworth, Z. Pei, C. Fitzgerald, and
__T. Jiang__, “Application of a Metallic Cap Layer to Control Cu TSV Extrusion”,*Proc. IEEE Electronic Component and Technology Conference (ECTC),*pp. 61-66 (2017)*.* - L. Spinella,
__T. Jiang__, J. Im, and P.S. Ho, “Synchrotron X-ray Microdiffraction Investigation of Scaling Effects on Plasticity and the correlation to TSV Extrusion”*Proc. IEEE Electronic Component and Technology Conference (ECTC),*pp. 752-757 (2017). - L. Spinella,
__T. Jiang__, M. Park, N. Tamura, J. Im, P.S. Ho, “Effect of Scaling Copper Through-Silicon Vias on Stress and Reliability for 3D Interconnects”,*Proc. 2016 IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC)*, pp. 80-82*(*2016)*.* __T. Jiang__, C. Wu, P. Su, P. Kim, C. Bassett, K. Sichak, J. Gandhi, J. Li, J. Im, R, Huang, and P. S. Ho, “Investigation of Thermo-mechanical Stresses and Reliability of 3D Die-Stack Structures by Synchrotron X-ray Micro-diffraction”,*Proc. IEEE Electronic Component and Technology Conference (ECTC)*, pp. 1718 – 1724 (2015)*.*__T. Jiang__, C. Wu, J. Im, R. Huang, and P.S. Ho, “Effect of Microstructure on Via Extrusion Profile and Reliability Implication for Copper Through-Silicon Vias (TSVs) Structures”,*Proc. IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC)*, pp. 377-380 (2014).__T. Jiang__, C. Wu, P. Su, P. Chia, L. Li, H.-Y. Son, M.-S. Suh, N.-S Kim, J. Im, R. Huang, and P.S. Ho, “Effect of High Temperature Storage on the Stress and Reliability of 3D Stacked Chip”,*Proc. IEEE Electronic Component and Technology Conference (ECTC)*, pp. 1122 – 1127 (2014).__T. Jiang__, S.K. Ryu, J. Im, R. Huang, and P.S. Ho, “Characterization of Thermal Stresses and Plasticity in Through-silicon Via Structures for Three-dimensional Integration”,*AIP Conf. Proc.*1601, 55 (2014).__T. Jiang__, S.K. Ryu, Q. Zhao, J. Im, P.S. Ho, and R. Huang, “Thermomechanical Characterization and Modeling for TSV Structures”,*AIP Conf. Proc.*1601, 148 (2014).__T. Jiang__, S.K. Ryu, J. Im, H.-Y Son, N.-S. Kim, R. Huang, and P.S. Ho, “Impact of Material and Microstructure on Thermal Stresses and Reliability of Through-Silicon Via (TSV) Structures”,*Proc. International Interconnect Technology Conference (IITC)*, pp. 1-3 (2013).__T. Jiang__, C.L. Wu, P. Su, X. Liu, P. Chia, L. Li, H.-Y. Son, N.-S. Kim, K.-Y. Byun, J.-S. Oh, J. Im, R. Huang, and P.S. Ho, “Characterization of Plasticity and Stresses in TSV Structures in Stacked Dies Using Synchrotron X-ray Microdiffraction”,*Proc. IEEE Electronic Component and Technology Conference (ECTC)*, pp. 641 – 647 (2013).__T. Jiang__, S.K. Ryu, Q. Zhao, J. Im, H.-Y. Son, K.-Y Byun, R. Huang and P.S. Ho, “Thermal stress Characteristics and Impact on Device Keep-out Zone for 3-D ICs Containing Through-silicon-vias”,*IEEE Symposium on VLSI Technology (VLSIT)*, pp. 103-104 (2012).__T. Jiang__, S.K. Ryu, Q. Zhao, J. Im, H.-Y. Son, K.-Y Byun, R. Huang, and P.S. Ho, “Measurement and Analysis of Thermal Stresses in 3-D Integrated Structures Containing Through-Silicon-Vias”,*Proc. IEEE International Interconnect Technology Conference (IITC)*, pp.1-3 (2012).__T. Jiang__, S.K. Ryu, Q. Zhao, J. Im, H.-Y. Son, K.-Y. Byun, R. Huang, and P.S. Ho, “Thermal Stress Characteristics and Reliability Impact On 3-D ICs Containing Through-Silicon-Vias”,*Proc. IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT),*pp.1-3 (2012).- Wang, S.-H. Chae, R. Dunne, Y. Takahashi, K. Mawatari, P. Steinmann, T. Bonifield,
__T. Jiang__, J. Im, P.S. Ho, “Effect Of Intermetallic Formation on Electromigration Reliability of TSV-Microbump Joints in 3D Interconnect”,*Proc. IEEE Electronic Component and Technology Conference (ECTC)*, pp. 319- 325 (2012).

BOOK CHAPTERS

- Chen,
__T. Jiang__, and X. Fan, “Die- and Package-Level Modeling and Characterization of Thermal and Thermal/Moisture Stresses in 3-D Packaging: Modeling and Characterization”,*3D Microelectronic Packaging: From Fundamentals to Applications*, Y. Li & D. Goyal Eds., pp 293-332 (2017). Springer International Publishing, Switzerland. - S.K. Ryu, T. Jiang, J. Im, R. Huang and P.S. Ho, “Thermal Stress in 3-D Packaging”,
*Encyclopedia of Thermal Stresses*, R.B. Hetnarski Ed., pp 5208-5217 (2014). Springer Dordrecht, Heidelberg, New York, London. - Fu-Zhai Cui and Teng-Fei Jiang, “Tissue-Engineered Bone”,
*Wiley Encyclopedia of Biomedical Engineering*, M. Akay Ed.,(2006). John Wiley & Sons, Hoboken, New Jersey.